1. Field
Example embodiments relate to layout schemes of power gating transistor switches, layout methods of power gating transistor switches, semiconductor devices including the power gating transistor switches, and power gating methods of the semiconductor devices. Also, example embodiments relate to layout schemes of power gating transistor switches, layout methods of power gating transistor switches, semiconductor devices including the power gating transistor switches, and power gating methods of the semiconductor devices in which a power voltage and/or a ground voltage may be sequentially applied and/or blocked to a logic circuit, without a separate device or devices, using poly resistors.
2. Description of Related Art
An important issue for mobile devices is low power consumption. Therefore, various low power methods are being developed. One of them is power gating.
Power gating turns power on to a power gating transistor switch to apply a power voltage (or a ground voltage) to a logic circuit including transistors having a relatively low threshold voltage at an active mode of the logic circuit in order to increase an operating speed of the logic circuit, and turns power off to the power gating transistor switch to block the power voltage (or the ground voltage) applied to the logic circuit at a sleep mode in order to reduce leakage current of the logic circuit.
To this end, metal-oxide semiconductor (MOS) transistors having a relatively high threshold voltage are serially connected between the power voltage (or the ground voltage) and the logic circuit. Power gating is very useful to reduce power consumption of a portable large scale integration (LSI) chip that stays quite longer at the active mode than the sleep mode.
FIG. 1 is a circuit diagram of a part of a related art power gating transistor switch 10. Referring to FIG. 1, the related art power gating transistor switch 10 comprises PMOS transistors P1, P2, P3, and P4 that are serially connected between a power voltage VDD and a virtual power voltage VDDV. The virtual power voltage VDDV is applied to a logic circuit (not shown) that performs a predetermined logic operation.
The power gating transistor switch 10 can comprise NMOS transistors (not shown) according to the location thereof. In this case, NMOS transistors (not shown) are serially connected between a ground voltage (not shown) and a virtual ground voltage (not shown).
At an active mode, i.e., when the power voltage VDD is applied to the logic circuit (not shown), the PMOS transistors P1, P2, P3, and P4 are turned on by a power gating enable signal PG_EN of logic low L. The power gating enable signal PG_EN indicates whether a semiconductor device is at the active mode or a sleep mode. The turned-on PMOS transistors P1, P2, P3, and P4 allow the virtual power voltage VDDV to be connected to the power voltage VDD.
In this case, since the logic circuit (not shown) includes low threshold voltage devices, the logic circuit can perform a high performance operation. An amount of leakage current is not quite greater than that of dynamic current, thereby reducing power consumption caused by the leakage current.
Meanwhile, at the sleep mode, the PMOS transistors P1, P2, P3, and P4 are turned off by the power gating enable signal PG_EN of logic high H, so that power is not supplied to the logic circuit (not shown).
However, the PMOS transistors P1, P2, P3, and P4 of the power gating transistor switch 10 are simultaneously turned on or off, causing switching noise. The switching noise can result in malfunction of the logic circuit (not shown).
FIG. 2 is a circuit diagram of a part of another related art power gating transistor switch 20. Referring to FIG. 2, the power gating transistor switch 20 comprises a control device in order to sequentially turn on or off PMOS transistors P1, P2, P3, and P4. The power gating transistor switch 20 further comprises delay buffers.
The power gating transistor switch 20 sequentially turns on or off the PMOS transistors P1, P2, P3, and P4 using delay buffers, thereby reducing or removing the switching noise occurred in the power gating transistor gate 10 of FIG. 1. However, the power gating transistor switch 20 needs delay buffers and an algorithm for controlling the delay buffers.
For example, the power gating transistor switch 20 involves an increase in chip area and/or control complexity.